Magnetic storage devices such as computer hard drives write binary information to and read binary information from a magnetic storage media (e.g., a magnetic disc comprising Fe.sub.2 O.sub.3, NiCo, etc.). Binary information is written to the magnetic storage media by changing the magnetization of domains within the media to either a first magnetization (e.g., representing a binary "1") or a second magnetization (e.g., representing a binary "0"). Written binary information is read from the magnetic storage media by rotating the magnetized media at a constant velocity and by sensing the time-changing flux produced by each magnetized domain.
Within each magnetic storage device, in addition to the magnetic storage media, a write head is provided that comprises an inductive coil for generating a two-directional or "bipolar" flux which changes the magnetization of the domains within the magnetic storage media between the first and second magnetizations. The bipolar flux is generated via a bipolar current driven through the inductive coil by a write driver circuit.
Typically, the speed of the write driver circuit that drives the inductive write head governs the maximum operating speed (e.g., the maximum read/write time) of a magnetic storage device; and the speed of a write driver circuit is the time required to switch the direction of the current flowing through the inductive coil of the write head as described below with reference to FIGS. 1A and 1B.
Magnetic storage devices typically employ a write driver circuit known as an H-driver circuit, such as the H-driver circuit 100 (hereinafter "conventional H-driver 100") of FIG. 1A. The conventional H-driver 100 drives a differential current through a write coil (e.g., write coil 102) coupled between a first differential output terminal OUT.sub.T (e.g., "Output True") and a second differential output terminal OUT.sub.C (e.g., "Output Complement") of the H-driver 100 to affect magnetization of a magnetic storage media (not shown) adjacent the write coil 102. Specifically, a differential input voltage applied between a first differential input terminal IN.sub.T (e.g., "Input True") and a second differential input terminal IN.sub.C (e.g., "Input Complement") of the H-driver 100 controls the direction of differential current flow through the write coil 102, and thus the magnetization written to the magnetic storage media (not shown).
A typical differential input voltage might be 500 millivolts centered at -2 volts, so that a "high" input voltage level on either input terminal IN.sub.T or IN.sub.C is -1.75 volts and a "low" input voltage level on either input terminal IN.sub.T or IN.sub.C is -2.25 volts. Other differential input voltages and center voltages may be employed.
The H-driver 100 further comprises a first pull-down transistor (Q.sub.1) 104 for pulling the output terminal OUT.sub.C to a low voltage level with respect to the output terminal OUT.sub.T (e.g., by sourcing current through the write coil 102 in a first direction as described below) and a second pull-down transistor (Q.sub.2) 106 for pulling the output terminal OUT.sub.T to a low voltage level with respect to the output terminal OUT.sub.C (e.g., by sourcing current through the write coil 102 in a second direction as describe below). The first pull-down transistor 104 has a base lead connected to the input terminal IN.sub.T, a collector lead connected to the output terminal OUT.sub.C and an emitter lead connected to a negative voltage rail (V.sub.ee) 108 via a first current source (J.sub.1) 110. The second pull-down transistor 106 has a base lead connected to the input terminal IN.sub.C, a collector lead connected to the output terminal OUT.sub.T and an emitter lead connected to the emitter lead of the first pull-down transistor 104 and to the first current source 110.
Also provided within the H-driver 100 are a first pull-up transistor (Q.sub.5) 112 for pulling the output terminal OUT.sub.C to a high voltage level with respect to the output terminal OUT.sub.T and a second pull-up transistor (Q.sub.6) 114 for pulling the output terminal OUT.sub.T to a high voltage level with respect to the output terminal OUT.sub.C. The first pull-up transistor 112 has a base lead connected to a positive voltage rail (V.sub.CC) 116 via a first pull-up resistor (R.sub.1) 118, a collector lead connected to the positive voltage rail 116 and an emitter lead connected to the output terminal OUT.sub.C via a first Schottky diode (D.sub.1) 120. The high D.C. voltage level for the output terminal OUT.sub.C, therefore, is approximately V.sub.CC minus the forward voltage of the first pull-up transistor 112's base-emitter junction and the forward voltage of the first Schottky diode 120 (neglecting the IR drop associated with the first pull-up resistor 118). The second pull-up transistor 114 has a base lead connected to the positive voltage rail 116 via a second pull-up resistor (R.sub.2) 122, a collector lead connected to the positive voltage rail 116 and an emitter lead connected to the output terminal OUT.sub.T via a second Schottky diode (D.sub.2) 124. The high D.C. voltage level for the output terminal OUT.sub.T, therefore, is approximately V.sub.CC minus the forward voltage of the second pull-up transistor 114's base-emitter junction and the forward voltage of the second Schottky diode 124 (neglecting the IR drop from the second pull-up resistor 122). The first and the second Schottky diodes 120 and 124 protect the base-emitter junctions of the first and the second pull-up transistors 112 and 114, respectively, from being reverse biased and damaged during switching of the current flow direction through the write coil 102 (as described below).
The H-driver 100 further comprises a third pull-down transistor (Q.sub.3) 126 and a fourth pull-down transistor (Q.sub.4) 128 for pulling to a low voltage level the base lead of the first pull-up transistor 112 and the base lead of the second pull-up transistor 114, respectively. The third pull-down transistor 126 has a base lead connected to the input terminal IN.sub.T, a collector lead connected to the base lead of the first pull-up transistor 112 and an emitter lead connected to the negative voltage rail 108 via a second current source (J.sub.2) 130. A third Schottky diode (D.sub.3) 132 is connected between the collector of the third pull-down transistor 126 (forming a first node 134) and ground for preventing the first node 134 from being pulled below ground by more than the forward voltage (e.g., about 0.4-0.5 volts) of the third Schottky diode 132.
The fourth pull-down transistor 128 has a base lead connected to the input terminal IN.sub.C, a collector lead connected to the base lead of the second pull-up transistor 114 and an emitter lead connected to the emitter lead of the third pull-down transistor 126 and to the second current source 130. A fourth Schottky diode (D.sub.4) 136 is connected between the collector of the fourth pull-down transistor 128 (forming a second node 138) and ground for preventing the second node 138 from being pulled below ground by more than the forward voltage (e.g., about 0.4-0.5 volts) of the fourth Schottky diode 136.
In operation, if a high voltage level is applied to the input terminal IN.sub.T and a low voltage level is applied to the input terminal IN.sub.C, the high voltage level applied to the input terminal IN.sub.T turns ON the first and the third pull-down transistors 104 and 126 by forward biasing each transistor's base-emitter junction. Currents J.sub.1 and J.sub.2 (from the first and second current sources 110 and 130, respectively) thereby are caused to flow through the first and the third pull-down transistors 104 and 126, respectively.
In steady-state, with the third pull-down transistor 126 ON, the first node 134 is pulled to a low voltage level (i.e., is pulled low), the Schottky diode 132 is forward biased and conducts, and the current J.sub.2 flowing through the third pull-down transistor 126 is split between the first pull-up resistor 118 and the third Schottky diode 132. Because the third Schottky diode 132 conducts, the voltage at the first node 134 is held slightly negative (e.g., at approximately the forward voltage of the third Schottky diode 132 below ground). With the first node 134 pulled low via the third pulled-down transistor 126, the base of the first pull-up transistor 112 also is pulled low, and the first pull-up transistor 112 is OFF.
The low voltage level applied to the input terminal IN.sub.C turns OFF the second and the fourth pull-down transistors 106 and 128. With the fourth pull-down transistor 128 OFF, only a small voltage drop (e.g., due to the base current from the second pull-up transistor 114) can exist across the second pull-up resistor 122. Therefore, the second node 138 is pulled to a high voltage level (i.e., is pulled high), the base-emitter junction of the second pull-up transistor 114 is forward biased (turning ON the second pull-up transistor 114), and the second Schottky diode 124 is forward biased. Accordingly, the current J.sub.1 from the first current source 110 flows from the positive voltage rail 116 through the second pull-up transistor 114, through the second Schottky diode 124, through the write coil 102 (in a first direction designated as the -y direction in FIG. 1A), through the first pull-down transistor 104 and through first current source 110 to the negative voltage rail 108. The flow of the current J.sub.1 through the write coil 102 in the first direction generates a magnetic flux that changes the magnetization of a domain within a magnetic storage media (not shown) adjacent the write coil 102 to a first magnetization (e.g., the first magnetization representing a binary "1") as the magnetic storage media is rotated.
Thereafter, to write a second magnetization to the magnetic storage media (not shown), the direction of the current flow through the write coil 102 is reversed (e.g., so the current J.sub.1 flows in the opposite or +y direction through the write coil 102) by applying a low voltage level to input terminal IN.sub.T and a high voltage level to the input terminal IN.sub.C. FIG. 1B is a schematic diagram of the H-driver 100 of FIG. 1A showing the current flow within the H-driver 100 when a low voltage level is applied to the input terminal IN.sub.T and a high voltage level is applied to the input terminal IN.sub.C.
With reference to FIG. 1B, in steady-state, with the input terminal IN.sub.C at a high voltage level and the input terminal IN.sub.T at a low voltage level, the H-driver 100 behaves as the inverted equivalent of the oppositely biased H-driver 100 of FIG. 1A. Specifically, the second and the fourth pull-up transistors 106 and 128 are ON so as to pull the output terminal OUT.sub.T and the base of the second pull-up transistor 114 low (turning OFF the second pull-up transistor 114), and the first and the third pull-down transistors 104 and 126 are OFF such that currents J.sub.1 and J.sub.2 flow through the second and the fourth pull-down transistors 106 and 128, respectively.
With the fourth pull-down transistor 128 ON, the second node 138 is pulled low, the Schottky diode 136 is forward biased and conducts, and the current J.sub.2 flowing through the fourth pull-up transistor 128 is split between the second pull-up resistor 122 and the fourth Schottky diode 136. Because the fourth Schottky diode 136 conducts, the voltage of the second node 138 is held slightly negative (e.g., at approximately the forward voltage of the fourth Schottky diode 136 below ground).
In steady-state, with the first and the third pull-up transistors 104 and 126 OFF, little current flows through the first pull-up resistor 118 so that the first node 134 is pulled high, the base-emitter junction of the first pull-up transistor 112 is forward biased (turning ON the first pull-up transistor 112), and the first Schottky diode 120 is forward biased. Accordingly, the current J.sub.1 flows from the positive voltage rail 116 through the first pull-up transistor 112, through the first Schottky diode 120, through the write coil 102 in the second direction (the +y direction) opposite the first direction, through the second pull-down transistor 106 and through the first current source 110 to the negative voltage rail 108. The flow of the current J.sub.1 through the write coil 102 in the second direction generates a magnetic flux that changes the magnetization of a domain within a magnetic storage media (not shown) adjacent the write coil 102 to a second magnetization (e.g., the second magnetization representing a binary "0") as the magnetic storage media is rotated.
As previously stated, the speed of a write driver circuit such as the H-driver 100 typically governs the maximum speed of a magnetic storage device employing the write driver circuit. The speed of the H-driver 100 is the time required to switch the direction of the current flowing through the write coil 102 between the first direction (FIG. 1A) and the second direction (FIG. 1B); and how quickly the current direction can change primarily depends on the voltage applied across the write coil 102 during current direction switching. Specifically, the time rate of change of the current flowing through the write coil 102 is governed by the equation: ##EQU1##
where J is the current flowing through the write coil 102, L is the inductance of the write coil 102 and V.sub.WC is the voltage applied across the write coil 102 by the H-driver 100 during current direction switching (i.e., the coil voltage V.sub.WC). As shown by equation (1), maximizing the coil voltage V.sub.WC maximizes the speed of current direction switching.
Up to a limit, the coil voltage V.sub.WC (and thus the current direction switching speed of the H-driver 100) can be increased by decreasing the resistance values of the first and the second pull-up resistors 118 and 122, and by increasing the current J.sub.2 supplied by the second current source 130. Decreasing the resistance values of the first and the second pull-up resistors 118 and 122 decreases the RC time constants of the current paths responsible for pulling high the first and the second nodes 134 and 138 (current path A and current path B, respectively, in FIGS. 1A and 1B), and thus allows each node to be pulled high faster. As will be further understood with reference to the detailed description of the preferred embodiments, quickly pulling high the first and the second nodes 134 and 138 can increase the coil voltage V.sub.WC during current direction switching (and thus the current direction switching speed of the H-driver 100) if the minimum node voltage level which the first and the second nodes 134 and 138 were pulled to prior to decreasing the resistance values of the first and the second pull-up resistors 118 and 122 (i.e., the minimum node voltage of the H-driver 100) is maintained. Increasing the current J.sub.2 compensates for the decreased resistance values of the first and the second pull-up resistors 118 and 122 (e.g., by keeping the IR drop across each pull-up resistor constant despite the decrease in the resistance value of the pull-up resistor), and maintains constant the minimum node voltage of the H-driver 100. With the first and the second nodes 134 and 138 being pulled high quickly and the minimum node voltage of the H-driver 100 maintained, the coil voltage V.sub.WC is increased, as is the current direction switching speed of the H-driver 100.
Increasing the current J.sub.2 increases the power consumption of the H-driver 100, which is especially problematic in low power applications (e.g., portable computing). Additionally, the higher currents within the H-driver 100 require the use of larger current switches (e.g., larger third and fourth pull-down transistors 126 and 128). The larger current switches have slower switching speeds that can effectively reduce the current direction switching speed of the H-driver 100.
Accordingly, a need exists for a method and apparatus for increasing the speed of magnetic storage device write driver circuitry. Such a method and apparatus will increase the overall operating speed of magnetic storage devices.